When a semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), is scaled down through various technology nodes, high-k gate dielectric layer and metal gate electrode layer are incorporated into the gate stack of the MOSFET to improve device performance with the decreased feature sizes. In addition, strained structures in source and drain (S/D) recess cavities of the MOSFET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, it is difficult to achieve enhanced carrier mobility for a field-effect transistor (FET) because strained materials can not deliver a given amount of strain into channel region of the FET, thereby increasing the likelihood of device instability and/or device failure. As the gate length and spacing between devices decrease, these problems are exacerbated.